1. Field of the Invention
The present invention relates to a clock delay circuit, and more particularly to a clock delay circuit in a DLL (Delay-Locked Loop) circuit to be mounted in a semiconductor memory device.
2. Description of the Related Art
To enable high-speed operation, some semiconductor memory devices output a data synchronous with both the rising and falling edges of clock. Semiconductor memory devices of this type are disclosed in JP-A-2001-056723, JP-A-2001-111394, JP-A-2003-101409, and JP-A-2004-171082.
A DLL circuit is mounted in the above-described semiconductor memory devices. The DLL circuit both generates data output clock QCLK_T for providing data signal DQ in synchronization with the rising edge of the clock and generates data output clock QCLK_B for providing data signal DQ in synchronization with the falling edge of the clock. The DLL circuit then provides a data signal DQ in synchronization with the rising edge of the clock based on data output clock QCLK_T and provides a data signal DQ in synchronization with the falling edge of the clock based on data output clock QCLK_B.
In the semiconductor memory device, the higher the frequency of the clock, the greater the effect that data signal DQ brought about by the jitter of data output clocks QCLK_T and QCLK_B generated in the DLL circuit. It is therefore a crucial issue in the design of a semiconductor memory device, to reduce of the jitter of data output clocks QCLK_T and QCLK_B.
FIG. 1 shows an example of the configuration of a typical DLL circuit, and FIG. 2 shows an example of the configuration of a clock delay circuit of the prior art in a DLL circuit.
As shown in FIG. 1, a typical DLL circuit includes: input buffer (IN) 101; clock delay circuits (Delay Lines) 102R and 102F; interpolator circuits (Interpolators) 103R and 103F; level shift circuit (Level Shifter) 104; output buffer (OUT) 105; replica circuits (Replicas) 106R and 106F; P/D (Phase/Detector) circuits 107R and 107F; Rise control circuit (Rise control) 108R; Fall control circuit (Fall control) 108F; Rise counter 109R; Fall counter 109F; predecoder circuit (Pre Dec) 110R and 110F; and 5-bit DAC (Digital Analog Converter) circuits 111R and 111F.
Input buffer 101 receives mutually complementary external clock signal CLK and external clock signal CLKB and provides internal clock signal ICLK_R for the Rise CLK and internal clock signal ICLK_F for the Fall CLK.
Clock delay circuit 102R provides delay clock signals OUTR_O and OUTR_E that are the delayed internal clock signal ICLK_R, and clock delay circuit 102F provides delay clock signals OUTF_O and OUTF_E that are the delayed internal clock signal ICLK_F.
Interpolator circuit 103R mixes delay clock signals OUTR_O and OUTR_E at a mix ratio that corresponds to bias voltage BIASRE/O. In addition, interpolator circuit 103F mixes delay clock OUTF_O and OUTF_E at a mix ratio that corresponds to bias voltage BIASFE/O.
Level shift circuit 104 generates data output clocks QCLK_T and QCLK_B based on the output from interpolator circuits 103R and 103F and converts the level of data output clocks QCLK_T and QCLK_B that have been generated. More specifically, level shift circuit 104 determines the rising edge of data output clock QCLK_T based on the rising edge of a signal obtained by mixing delay clock signals OUTR_O and OUTR_E. Level shift circuit 104 determines the rising edge of data output clock QCLK_B based on the rising edge of a signal obtained by mixing delay clock signals OUTF_O and OUTF_E. In addition, since clock delay circuits 102R and 102F, interpolator circuits 103R and 103F, and 5-bit DAC circuits 111R and 111F are influenced by voltage fluctuation and noise when they employ an external voltage, they employ an internal voltage (constant voltage). Other constituent elements employ an external voltage. Level shift circuit 104 therefore carries out the above-described level conversion operation.
Output buffer 105 both provides data signal DQ in synchronization with the rising edge of the clock based on data output clock QCLK_T and provides data signal DQ in synchronization with the falling edge of the clock based on data output clock QCLK_B.
Replica circuit 106R generates a replica signal RCLK of data output clock QCLK_T. Replica circuit 106F generates a replica signal FCLK of data output clock QCLK_B.
P/D circuit 107R compares the phase of the rising edges of external clock signal CLK and the phase of replica signal RCLK to determine whether the phase of replica signal RCLK is behind or in advance of external clock signal CLK. P/D circuit 107F compares the phase of the rising edges of external clock signal CLKB and replica signal FCLK to determine whether the phase of replica signal FCLK is behind or in advance of external clock signal CLKB.
Rise control circuit 108R controls the count values of Rise counter 109R based on the determination result of P/D circuit 107R. More specifically, Rise control circuit 108R increments the count value when the phase of replica signal RCLK leads relative to external clock signal CLK to delay the phase of replica signal RCLK. On the other hand, when the phase of replica signal RCLK lags relative to external clock signal CLK, Rise control circuit 108R decrements the count value to advance the phase of replica signal RCLK. Fall control circuit 108F controls the count values of Fall counter 109F based on the determination result of P/D circuit 107F. The control procedure of Fall control circuit 108F is the same as that of Rise control circuit 108R.
Rise counter 109R is an UP/DOWN counter whose count value is controlled by Rise control circuit 108R. The upper order five bits of the count value of Rise counter 109R are provided to predecoder circuit 110R as the values to determine the amount of delay in clock delay circuit 102R, and the lower order five bits are provided to 5-bit DAC circuit 111R as values to determine the mix ratio of delay clock signals OUTR_O and OUTR_E in interpolator circuit 103R. In addition, Fall counter 109F is an UP/DOWN counter whose count value is controlled by Fall control circuit 108F. The upper order five bits of the count value of Fall counter 109F are provided to predecoder circuit 110F as values to determine the amount of delay in clock delay circuit 102F, and the lower order five bit are provided to 5-bit DAC circuit 111F as values to determine the mix ratio of delay clock signals OUTF_O and OUTF_E in interpolator circuit 103F.
Predecoder circuit 110R carries out a process for predecoding the upper order five bits of the count value of Rise counter 109R, and provides predecoding signal PREDECR to determine the amount of delay in clock delay circuit 102R. Predecoder circuit 110F carries out a process for predecoding the upper order five bits of the count value of Fall counter 109F and provides predecoding signal PREDECF to determine the amount of delay in clock delay circuit 102F.
5-bit DAC circuit 111R converts the lower order five bits of the count value of Rise counter 109R from a digital signal to an analog signal, and to generate and provide bias voltage BIASRE/O to determine the mix ratio of delay clock signals OUTR_O and OUTR_E. 5-bit DAC circuit 111F receives the lower order five bits of the count value of Fall counter 109F and generates and provides bias voltage BIASFE/O to determine the mix ratio of delay clock signals OUTF_O and OUTF_E.
In the DLL circuit that is configured as described above, rough adjustment of the amount of delay of internal clocks ICLK_R and ICLK_F that are produced from external clocks CLK and CLKB is performed by the counter control implemented by clock delay circuits 102R and 102F. Thereby, delay clocks OUTR_O, OUTR_E, OUTF_O, and OUTF_E having a fixed delay amounts are provided from clock delay circuits 102R and 102F. Delay clocks OUTR_O and OUTR_E, and OUTF_O and OUTF_E are mixed by interpolator circuits 103R and 103F for fine adjustment of the delay amounts. Level shift circuit 104 generates and provides data output clocks QCLK_T and QCLK_B to provide data signal DQ in accordance with external clocks CLK and CLKB based on the output from interpolator circuits 103R and 103F.
As shown in FIG. 2, a clock delay circuit of the prior art includes: delay circuit section 41R, selection circuit section 42R, delay circuit section 41F, and selection circuit section 42F.
Delay circuit section 41R and selection circuit section 42R constitute Rise CLK clock delay circuit 102R shown in FIG. 1. Delay circuit section 41R provides a plurality of delay clocks produced by delaying internal clock signal ICLK_R with each delay clock having a different delay amount. Selection circuit section 42R arbitrarily selects any one of a plurality of delay clocks that have been provided from delay circuit section 41R, and provides the selected delay clocks as delay clocks OUTR_O and OUTR_E.
Delay circuit section 41F and selection circuit section 42F constitute Fall CLK clock delay circuit 102F shown in FIG. 1. Delay circuit section 41F provides a plurality of delay clocks produced by delaying internal clock ICLK_F with each delay clock having a different delay amount. Selection circuit section 42F arbitrarily selects any one of a plurality of delay clocks that have been provided from delay circuit section 41F and provides the selected delay clocks as delay clock signals OUTF_O and OUTF_E.
Since the Rise CLK circuit and the Fall CLK circuit are of the same configuration, only the Fall CLK circuit configuration will be explained below.
Delay circuit section 41F is of a configuration in which a plurality of delay circuits 411 for delaying internal clock ICLK_F by fixed delay amounts are connected in cascades. The amounts of delay of the delay clocks that are provided from each of the plurality of delay circuits 411 thus differ from each other.
Each of delay circuits 411 includes inverter NV 412, capacitor (constituted by an NMOS transistor in FIG. 2) 413, and capacitor (constituted by a PMOS transistor in FIG. 2) 414. In this way, delay circuit 411 adjusts the fixed delay amount by providing a capacitance load by means of capacitors 413 and 414 in the output part of inverter NV 412.
Selection circuit section 42F is of a configuration in which a plurality of selection circuits 421 are connected in cascades, these selection circuits 421 being associated with the plurality of delay circuits 411, for selecting delay clocks that are provided from the delay circuits 411 with which they are associated, and for providing the selected delay clocks as delay clocks OUTF_O and OUTF_E. In selection circuit section 42F, moreover, a delay clock that has been selected by any of selection circuits 421 that are of odd-numbered stages is provided as delay clock OUTF_O, and a delay clock that has been selected by any of selection circuits 421 that are of even-numbered stages is provided as delay clock OUTF_E.
Each of selection circuit 421 includes: NAND element NA 422, inverter NV 423, and clocked inverters CN 424 and 425.
For example, the following operations are carried out in second-stage selection circuit 421, which is an even-numbered stage, among selection circuits 421 that makes up selection circuit section 42F of FIG. 2. NAND element NA 422 calculates the NAND of both predecoding signal PREDECF<2> from predecoder circuit 110F to selection circuit 421 of its own stage (second stage) and predecoding signal PREDECF<1> from predecoder circuit 110F to selection circuit 421 of the preceding stage (first stage). Inverter NV 423 inverts and provides the output of NAND element NA 422. Clocked inverter CN 424 inverts and provides the delay clock from selection circuit 421 of the next even-numbered stage (fourth stage) in accordance with the inverted output of NAND element NA 422. Clocked inverter CN 425 inverts and provides the delay clock from delay circuit 411 that corresponds to its own stage (second stage) in accordance with the output of NAND element NA 422. Thus, selection circuit 421 is of a configuration that provides a delay clock that has been inverted and provided from either of clocked inverters CN 424 or 425 according to predecoding signal PREDECF that is received from the outside. In addition, selection circuits 421 are connected together by way of inverters.
As shown in FIG. 3, the following explanation regards signal waveforms in each section (refer to the block diagram of FIG. 1) of the DLL circuit in which the clock delay circuit of the prior art shown in FIG. 2 has been provided. In the following description, each of inverters NV 412 in delay circuits 411 of (m−1)th stage, mth stage, and (m+1)th stage of FIG. 2 are referred to as inverters NV #0, NV#1, and NV#2, respectively. In addition, each of clocked inverters CN 425 in selection circuit 421 of (m−1)th stage, mth stage, and (m+1)th stage of FIG. 2 are referred to as clocked inverter CN #0, CN#1, and CN#2, respectively; and NAND elements NA 422 of (m−1)th stage, mth stage, and (m+1)th stage of FIG. 2 are referred to as NAND elements NA#0, NA#1, and NA#2, respectively.
In FIG. 3, predecoding signal PREDECF<m−1> is “HIGH” in the interval up to time t1, and the other predecoding signals are all “LOW.” In other words, select signal SELFB<m−1> that is provided from (m−1)th NAND element NA#0 and select signal SELFB<m> that is provided from mth NAND element NA#1 are “LOW,” and the other select signals are all “HIGH.” As a result, (m−1)th clocked inverter CN#0 and mth clocked inverter CN#1 are selected. In this case, the output of (m−1)th inverter NV#0 is provided as delay clock OUTF_O, and the output of mth inverter NV#1 is provided as delay clock OUTF_E. Delay clocks OUTR_O and OUTR_E are also provided from Rise CLK selection circuit section 42R by the same operations. Delay clocks OUTR_O and OUTR_E are mixed by interpolator circuit 103R at a mix ratio that corresponds to bias voltage BIASRE/O. In this way, data output clock QCLK_T is generated for providing data signal DQ in synchronization with the rising edge. Delay clocks OUTF_O and OUTF_E are also mixed by interpolator circuit 103F at a mix ratio that corresponds to bias voltage BIASFE/O. In this way, data output clock QCLK_B is generated for providing data signal DQ in synchronization with the falling edge.
Subsequently, when the mix ratio for interpolator circuits 103R and 103F is OUTF_E: OUTF_O=100%:0%, predecoding signal PREDECF<m> at time t1 is “HIGH,” and the other predecoding signals are all “LOW.” In other words, select signal SELFB<m> that is provided from mth NAND element NA#1 and select signal SELFB<m+1> that is provided from (m+1)th NAND element NA#2 are both “LOW,” and the other select signals are all “HIGH.” As a result, mth clocked inverter CN#1 and (m+1)th clocked inverter CN#2 are selected, and (m−1)th clocked inverter CN#0 is not selected. At this time, when the rising edge of the delay clock at node A that corresponds to the output portion of (m−1)th inverter NV#0 coincides with the timing of the occurrence of the noise that accompanies switching of select signal SELFB<m−1>, jitter is produced at node A. This jitter is then propagated to node B that corresponds to the output portion of mth inverter NV#1, delay clock OUTF_E, and data output clock QCLK_B.
Similarly, when the mix ratio for interpolator circuits 103R and 103F is OUTF_E: OUTF_O=100%: 0%, select signal SELFB<m−1> that is provided from (m−1)th NAND element NA#0 and select signal SELFB<m> that is provided from mth NAND element NA#1 are again “LOW” at time t2, and the other select signals are all “HIGH.” As a result, (m−1)th clocked inverter CN#0 and mth clocked inverter CN#1 are selected, and (m+1)th clocked inverter CN#2 is not selected. At this time, when the rising edge of delay clock at node A coincides with the timing of the occurrence of noise that accompanies switching of select signal SELFB<m−1>, jitter is produced at node A. This jitter is then propagated to node B, delay clock OUTF_E, and data output clock QCLK_B.
Focusing on the delay clock at node A, noise occurs and the load fluctuates according to whether clocked inverter CN#1 of (m−1)th selection circuit 421 is in a selected state or nonselected state, whereby the amount of delay of (m−1)th delay circuit 411 varies, and this serves as a cause of jitter.
As described in the foregoing explanation, there exists a problem with a clock delay circuit of the prior art that jitter occurs when switching a delay clock signal that is selected in a selection circuit section, and this jitter is propagated through the delay circuit section.